SAN FRANCISCO — Executives and technologists put a positive spin on the increasing cost and complexity of scaling semiconductors in opening talks at the International Solid-State Circuits Conference (ISSCC) here. They rallied several hundred chip designers at this annual gathering to think out of the box.

“The ending of Moore’s law and Denard scaling means that new innovations are needed in instruction set architectures … I think we are entering another renaissance in computer architecture,” said David A. Paterson, professor emeritus at the University of California-Berkeley, noting that venture capitalists spent as much as $1.5 billion on chip startups last year.

“The incoming class of Ph.D. candidates is the best we can remember, and undergrads are getting excited about designing hardware again — neural networks a big part of it,” he said, citing the Tensorflow Processor Unit that he contributed to at Google and the RISC-V architecture that he helped launch.

“Moore’s law has been, in some ways, shackles leading us to multimillion-dollar masks and multibillion-dollar wafer fabs … the Moore’s law era was relatively constrained, the future was calibrated … now we can get off that path, look around, and really do some interesting things together,” said Vince Roche, chief executive of Analog Devices Inc. (ADI), in his keynote.

Roche called for applications-led innovations across multiple dimensions including materials, packaging, and software. He described three ADI products as examples.

ADI’s chip-scale pH sensor combines semiconductor processes such as electroplating, wafer bonding, and microfludic channels. The micro-module packaging of Linear Technologies, now part of ADI, handles 100-A power loads that required 10 modules a decade ago. In addition, ADI combines analytics and signal processing in a smart power meter to detect and reduce a $96 billion/year problem that utilities face with power theft.

“We invest in chemists, cryptographers, and even physicians to a fuller understanding of applications and market,” he said.

For his part, Patterson noted that the RISC-V Foundation has now attracted more than 100 members supporting the open instruction set architecture.

“I can’t believe RISC is still the best idea in processor architecture, but it is,” he said in a brief overview of the last 50 years of computing. “Our modest goal is to become world-dominating and be the ISA you run every day.”

Intel CPU performance in SpecIntCPU is rising at just three percent/year, said Patterson. Source: Computer Architecture: A Quantitative Approach, 2018.

Intel CPU performance in SpecIntCPU is rising at just three percent/year, said Patterson. Source: Computer Architecture: A Quantitative Approach, 2018.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times Circle me on Google+

Related posts:


Click here to open external link

With Moore's law ending, ISSCC keynotes call for creativity in chip design